Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.
Pengyu LiuZihan ZhangChen YinLiyan ChenJianfei JiangQin WangZhigang MaoNaifeng JingPublished in: FPL (2023)
Keyphrases
- signal processor
- pipeline architecture
- spatial and temporal
- spatio temporal
- real time
- management system
- spatial information
- parallel architecture
- low cost
- spatial data
- spatial distribution
- loosely coupled
- digital signal processors
- array processor
- single chip
- architectural design
- network architecture
- design considerations
- scientific computing
- layered architecture
- computation intensive
- space time
- processor array
- web services
- knowledge base