Weiguang Sheng

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 25

Top Topics

Reconfigurable Architecture

Activation Function

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Zelong Yuan, Siwei Yuan, Pengyu Liu, Chen Yin, Lei Xu, Weiguang Sheng, Naifeng Jing
A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm. ISCAS (2024)
Duo Yu, Ang Li, Naifeng Jing, Jianfei Jiang, Weiguang Sheng, Qin Wang
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. ACM Great Lakes Symposium on VLSI (2024)
Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. ASICON (2023)
Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng
An Efficient near-Bank Processing Architecture for Personalized Recommendation System. ASP-DAC (2023)
Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang
RTMDet-R2: An Improved Real-Time Rotated Object Detector. PRCV (12) (2023)
Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. ICCD (2023)
Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao
A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. 19 (2022)
Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. DATE (2021)
Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing
A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. BigDataSecurity (2021)
Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. DATE (2021)
Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. ACM Great Lakes Symposium on VLSI (2020)
Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao
Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 31 (9) (2020)
Yijia Zhang, Weiguang Sheng, Jian-Fei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao
Priority Branches for Ship Detection in Optical Remote Sensing Images. Remote. Sens. 12 (7) (2020)
Qin Wang, Fengyi Shen, Linyao Shen, Jia Huang, Weiguang Sheng
Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network. J. Digit. Imaging 32 (6) (2019)
Zhongyuan Zhao, Hyoukjun Kwon, Sachit Kuhar, Weiguang Sheng, Zhigang Mao, Tushar Krishna
mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. ISPASS (2019)
Qin Wang, Zechen Liu, Jian-Fei Jiang, Naifeng Jing, Weiguang Sheng
A New Cellular-Based Redundant TSV Structure for Clustered Faults. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. ReConFig (2018)
Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao
Optimizing the data placement and transformation for multi-bank CGRA computing system. DATE (2018)
Haryadi S. Gunawi, Riza O. Suminto, Russell Sears, Casey Golliher, Swaminathan Sundararaman, Xing Lin, Tim Emami, Weiguang Sheng, Nematollah Bidokhti, Caitie McCaffrey, Gary Grider, Parks M. Fields, Kevin Harms, Robert B. Ross, Andree Jacobson, Robert Ricci, Kirk Webb, Peter Alvaro, H. Birali Runesha, Mingzhe Hao, Huaicheng Li
Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems. FAST (2018)
Haryadi S. Gunawi, Riza O. Suminto, Russell Sears, Casey Golliher, Swaminathan Sundararaman, Xing Lin, Tim Emami, Weiguang Sheng, Nematollah Bidokhti, Caitie McCaffrey, Deepthi Srinivasan, Biswaranjan Panda, Andrew Baptist, Gary Grider, Parks M. Fields, Kevin Harms, Robert B. Ross, Andree Jacobson, Robert Ricci, Kirk Webb, Peter Alvaro, H. Birali Runesha, Mingzhe Hao, Huaicheng Li
Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems. ACM Trans. Storage 14 (3) (2018)
Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li
A static-placement, dynamic-issue framework for CGRA loop accelerator. DATE (2017)
Jian-Fei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. 25 (10) (2016)
Weiguang Sheng, Jian-Fei Jiang, Zhigang Mao
Parallel SER analysis for combinational and sequential standard cell circuits. Microelectron. J. 50 (2016)
Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao
Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig (2015)
Xiang Tao, Yongxin Zhu, Yishu Mao, Han Song, Mengyun Liu, Xinyi Liu, Weiguang Sheng, Weiwei Shi
Designing ARINC653 Partition Constrained Scheduling for Secure Real Time Embedded Avionics. CSCloud (2015)
Jian-Fei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao
A contactless testing methodology for pre-bond interposer. MWSCAS (2015)
Weiguang Sheng, Zhongyuan Zhao, Zhigang Mao
Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. PRDC (2015)
Fengshuo Tian, Weiguang Sheng, Weifeng He
An automatic translation and parallelization system for general purpose reconfigurable processor. ASICON (2015)
Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. ASICON (2013)
Weiguang Sheng, Weifeng He, Jian-Fei Jiang, Zhigang Mao
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. IPDPS Workshops (2012)
Yifan Zhou, Weiguang Sheng, Xie Liu, Weifeng He, Zhigang Mao
Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. ASICON (2011)
Hao Wang, Weiguang Sheng, Weifeng He
Automatic compilation flow for a coarse-grained reconfigurable processor. ASICON (2011)
Weiguang Sheng, Liyi Xiao, Zhigang Mao
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. DAC (2009)
Weiguang Sheng, Liyi Xiao, Zhigang Mao
Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns. PRDC (2008)
Weiguang Sheng, Liyi Xiao, Zhigang Mao
A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis. ICECS (2008)
Weiguang Sheng, Liyi Xiao, Zhigang Mao
An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. DELTA (2008)