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Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage.

Yongming DingWei JinGuanghui HeWeifeng He
Published in: ASICON (2017)
Keyphrases
  • low voltage
  • high speed
  • cmos technology
  • power consumption
  • low power
  • power management
  • real time
  • design considerations
  • power line
  • low cost
  • random access memory