Jie Li

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 18

Top Topics

High Reliability

Error Correction

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

He Liu, Jiaqiang Li, Liyi Xiao, Tianqi Wang, Jie Li
SET-detection low complexity burst error correction codes for SRAM protection. Integr. 98 (2024)
Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang
A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Hongchen Li, Liyi Xiao, Chunhua Qi, Jie Li
Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (10) (2021)
Jie Li, Pedro Reviriego, Shanshan Liu, Liyi Xiao, Fabrizio Lombardi
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH). Integr. 81 (2021)
Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Linzhe Li
An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA. IEEE Trans. Reliab. 69 (2) (2020)
Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi
Scheme for periodical concurrent fault detection in parallel CRC circuits. IET Comput. Digit. Tech. 14 (2) (2020)
Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Tianqi Wang
Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs. ICICDT (2019)
Hongchen Li, Liyi Xiao, Jie Li, He Liu
Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology. ASICON (2019)
Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit. ASICON (2019)
Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network. ASICON (2019)
Xuebing Cao, Liyi Xiao, Jie Li, Rongsheng Zhang, Shanshan Liu, Jinxiang Wang
A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Chunhua Qi, Jiaqiang Li, Mingjiang Wang
A fast fault injection platform of multiple SEUs for SRAM-based FPGAs. Microelectron. Reliab. 82 (2018)
Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Jiaqiang Li, Jinxiang Wang
Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm. IOLTS (2018)
Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Costas Argyrides, Jie Li
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li, Tianqi Wang
A method to estimate cross-section of circuits at RTL levels. ASICON (2017)
Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao
Low redundancy matrix-based codes for adjacent error correction with parity sharing. ISQED (2017)
Rongsheng Zhang, Liyi Xiao, Jie Li
A fast and accurate fault injection platform for SRAM-based FPGAs. ASICON (2017)
Liyi Xiao, Jiaqiang Li, Jie Li, Jing Guo
Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories. ISQED (2015)