Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology.

Hongchen Li Liyi Xiao Jie Li He Liu

Published in: ASICON (2019)

Keyphrases

cost effective
cmos technology
cost effectiveness
power dissipation
low power
low cost
power consumption
flip flops
spl times
data center
parallel processing
design considerations
input output
digital signal processing
case study
design process
hidden markov models
pattern recognition