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A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).

Xuebing CaoLiyi XiaoJie LiRongsheng ZhangShanshan LiuJinxiang Wang
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019)
Keyphrases
  • logic circuits
  • error analysis
  • error estimation
  • real time
  • multi channel
  • event driven