Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations.

Chunmei Yang Hailong Jiao

Published in: ICICDT (2019)

Keyphrases

low power
error compensation
logic circuits
power consumption
high speed
low cost
power dissipation
single chip
high power
low power consumption
digital signal processing
vlsi circuits
cmos technology
vlsi architecture
phase shifting
gate array
structured light
power reduction
wireless transmission
data flow