An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator.

Ming Liu Yifan He Hailong Jiao

Published in: APCCAS (2022)

Keyphrases

systolic array
convolutional neural network
reconfigurable architecture
data flow
parallel architecture
face detection
hardware implementation
parallel implementation
neural network
floating point
field programmable gate array
lookup table
database
database systems
detection method
inverse halftoning