An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit.

Jiacong Sun Hao Guo Geng Li Hailong Jiao

Published in: IEEE J. Solid State Circuits (2022)

Keyphrases

low voltage
random access memory
cmos technology
high speed
design considerations
power line
low power
power management
low cost
parallel processing
leakage current
response time
power consumption