Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits.
José Pineda de GyvezHans TuinhoutPublished in: IEEE J. Solid State Circuits (2004)
Keyphrases
- low voltage
- leakage current
- mixed signal
- cmos technology
- circuit design
- power line
- vlsi circuits
- random access memory
- design considerations
- low power
- analog vlsi
- silicon dioxide
- power supply
- power management
- delay insensitive
- cmos image sensor
- high speed
- low cost
- parallel processing
- power dissipation
- electrical properties
- analog to digital converter