Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.
Mahendra RathorAditya AnshulK. BharathRahul ChaurasiaAnirban SenguptaPublished in: Comput. Electr. Eng. (2023)
Keyphrases
- intellectual property
- high level synthesis
- parallel architecture
- multi core processors
- hardware implementation
- patent search
- patent information
- design space exploration
- digital images
- clef ip
- parallel architectures
- e government
- processor core
- watermarking scheme
- computer architecture
- design process
- computer systems
- information technology
- watermarking algorithm
- patent documents
- software components
- artificial intelligence
- general purpose processors