Ad J. van de Goor

Publication Activity (10 Years)

Years Active: 1969-2011
Publications (10 Years): 0

Publications

Ad J. van de Goor, Said Hamdioui, Halil Kukner
Generic, orthogonal and low-cost March Element based memory BIST. ITC (2011)
Ad J. van de Goor, Said Hamdioui
MBIST architecture framework based on orthogonal constructs. IDT (2010)
Ad J. van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev
Low-cost, customized and flexible SRAM MBIST engine. DDECS (2010)
Ad J. van de Goor, Georgi Gaydadjiev, Said Hamdioui
Memory testing with a RISC microcontroller. DATE (2010)
Said Hamdioui, Ad J. van de Goor
Advanced embedded memory testing: Reducing the defect per million level at lower test cost. DDECS (2010)
Ad J. van de Goor, Said Hamdioui, Georgi Gaydadjiev
Using a CISC microcontroller to test embedded memories. DDECS (2010)
Ad J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars
New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. Asian Test Symposium (2009)
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georg Mueller
Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs. ITC (2008)
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Sultan M. Al-Harbi
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor
Space of DRAM fault models and corresponding testing. DATE (2006)
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor
Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Trans. Computers 55 (12) (2006)
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath
DRAM-Specific Space of Memory Tests. ITC (2006)
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Rob Wadsworth
Impact of stresses on the fault coverage of memory tests. MTDT (2005)
Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van de Goor
Framework for Fault Analysis and Test Generation in DRAMs. DATE (2005)
Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars
The Effectiveness of the Scan Test and Its New Variants. MTDT (2004)
Zaid Al-Ars, Ad J. van de Goor
Soft Faults and the Importance of Stresses in Memory Testing. DATE (2004)
Ad J. van de Goor, Said Hamdioui, Rob Wadsworth
Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. ITC (2004)
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor
Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. VTS (2004)
Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor
Memory Fault Modeling Trends: A Case Study. J. Electron. Test. 20 (3) (2004)
Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor
The State-of-Art and Future Trends in Testing Embedded Memories. MTDT (2004)
Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor
Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. MTDT (2004)
Ad J. van de Goor
An Industrial Evaluation of DRAM Tests. IEEE Des. Test Comput. 21 (5) (2004)
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (5) (2004)
Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars
Tests for address decoder delay faults in RAMs due to inter-gate opens. ETS (2004)
Zaid Al-Ars, Ad J. van de Goor
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. IEEE Trans. Computers 52 (3) (2003)
M. J. Geuzebroek, Ad J. van de Goor
TPI for improving PR fault coverage of Boolean and three-state circuits. ETW (2003)
Ivo Schanstra, Ad J. van de Goor
Consequences of RAM Bitline Twisting for Test Coverage. DATE (2003)
Ad J. van de Goor, Issam B. S. Tlili
A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories. IEEE Trans. Computers 52 (10) (2003)
Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor
Importance of dynamic faults for new SRAM technologies. ETW (2003)
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers
March SL: A Test For All Static Linked Memory Faults. Asian Test Symposium (2003)
Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. DATE (2003)
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor
A Fault Primitive Based Analysis of Linked Faults in RAMs. MTDT (2003)
Zaid Al-Ars, Ad J. van de Goor
Test generation and optimization for DRAM cell defects using electrical simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (10) (2003)
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. J. Electron. Test. 19 (2) (2003)
Said Hamdioui, Ad J. van de Goor, Mike Rodgers
Detecting Intra-Word Faults in Word-Oriented Memories. VTS (2003)
Zaid Al-Ars, Ad J. van de Goor
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. Asian Test Symposium (2003)
Zaid Al-Ars, Ad J. van de Goor
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. MTDT (2003)
Ad J. van de Goor, Ivo Schanstra
Address and Data Scrambling: Causes and Impact on Memory Tests. DELTA (2002)
Said Hamdioui, Ad J. van de Goor, Mike Rodgers
March SS: A Test for All Static Simple RAM Faults. MTDT (2002)
Zaid Al-Ars, Ad J. van de Goor
Modeling Techniques and Tests for Partial Faults in Memory Devices. DATE (2002)
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor
Testing Static and Dynamic Faults in Random Access Memories. VTS (2002)
M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. ITC (2002)
Zaid Al-Ars, Ad J. van de Goor
Approximating Infinite Dynamic Behavior for DRAM Cell Defects. VTS (2002)
Said Hamdioui, Ad J. van de Goor
Thorough testing of any multiport memory with linear tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (2) (2002)
Said Hamdioui, Ad J. van de Goor
Efficient Tests for Realistic Faults in Dual-Port SRAMs. IEEE Trans. Computers 51 (5) (2002)
Ad J. van de Goor, Magdy S. Abadir, Alan Carlin
Minimal Test for Coupling Faults in Word-Oriented Memories. DATE (2002)
Zaid Al-Ars, Ad J. van de Goor
DRAM Specific Approximation of the Faulty Behavior of Cell Defects. Asian Test Symposium (2002)
Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter
A Memory Specific Notation for Fault Modeling. Asian Test Symposium (2001)
Serge N. Demidenko, Ad J. van de Goor, S. Henderson, P. Knoppers
Simulation and Development of Short Transparent Tests for RAM. Asian Test Symposium (2001)
Zaid Al-Ars, Ad J. van de Goor
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. MTDT (2001)
Matthias Klaus, Ad J. van de Goor
Tests for Resistive and Capacitive Defects in Address Decoders. Asian Test Symposium (2001)
Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers
Realistic Fault Models and Test Procedures for Multi-Port SRAMs. MTDT (2001)
Zaid Al-Ars, Ad J. van de Goor
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. DATE (2001)
Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers
Detecting Unique Faults in Multi-port SRAMs. Asian Test Symposium (2001)
Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter
Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. ITC (2001)
Said Hamdioui, Ad J. van de Goor
An experimental analysis of spot defects in SRAMs: realistic fault models and tests. Asian Test Symposium (2000)
Zaid Al-Ars, Ad J. van de Goor
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. Asian Test Symposium (2000)
Said Hamdioui, Ad J. van de Goor
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy. J. Electron. Test. 16 (5) (2000)
Said Hamdioui, Ad J. van de Goor, Mike Rodgers, David Eastwick
March Tests for Realistic Faults in Two-Port Memories. MTDT (2000)
Ad J. van de Goor, A. Paalvast
Industrial evaluation of DRAM SIMM tests. ITC (2000)
Ad J. van de Goor, Zaid Al-Ars
Functional Memory Faults: A Formal Notation and a Taxonomy. VTS (2000)
M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor
Test point insertion for compact test sets. ITC (2000)
Said Hamdioui, Ad J. van de Goor
Port interference faults in two-port memories. ITC (1999)
M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor
Illegal State Space Identification for Sequential Circuit Test Generation. DATE (1999)
Ad J. van de Goor, J. de Neef
Industrial Evaluation of DRAM Tests. DATE (1999)
Ad J. van de Goor, Ivo Schanstra
Industrial evaluation of stress combinations for march tests applied to SRAMs. ITC (1999)
Ad J. van de Goor, J. E. Simonse
Defining SRAM Resistive Defects and Their Simulation Stimuli. Asian Test Symposium (1999)
Said Hamdioui, Ad J. van de Goor
March Tests for Word-Oriented Two-Port Memories. Asian Test Symposium (1999)
Daniel P. Van der Velde, Ad J. van de Goor
Designing a Memory Module Tester. MTDT (1999)
M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor
Testability of the Philips 80C51 micro-controller. ITC (1999)
M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor
Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. Asian Test Symposium (1999)
R. D. L. Stout, Ad J. van de Goor, R. E. Wolff
Automatic fault localization at chip level. Microprocess. Microsystems 22 (1) (1998)
Said Hamdioui, Ad J. van de Goor
Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. Asian Test Symposium (1998)
J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor
Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. Asian Test Symposium (1998)
Ad J. van de Goor, Said Hamdioui
Fault Models and Tests for Two-Port Memories. VTS (1998)
Ad J. van de Goor, Issam B. S. Tlili
March Tests for Word-Oriented Memories. DATE (1998)
Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. ITC (1998)
Said Hamdioui, Ad J. van de Goor
Consequences of port restrictions on testing two-port memories. ITC (1998)
Ad J. van de Goor
Answers to the Key Issues. Asian Test Symposium (1998)
Ad J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk
March LA: a test for linked memory faults. ED&TC (1997)
Ad J. van de Goor, Issam B. S. Tlili
Disturb Neighborhood Pattern Sensitive Fault. VTS (1997)
Ad J. van de Goor, Mike Lin
The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers. ITC (1997)
M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor
Sequential Test Generation with Advanced Illegal State Search. ITC (1997)
Ad J. van de Goor, Georgi Gaydadjiev
Realistic Linked Memory Cell Array Faults. Asian Test Symposium (1996)
J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor
Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. Asian Test Symposium (1996)
V. G. Mikitjuk, V. N. Yarmolik, Ad J. van de Goor
RAM Testing Algorithm for Detection Linked Coupling Faults. ED&TC (1996)
M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor
Accelerated Compact Test Set Generation for Three-State Circuits. ITC (1996)
Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik
March LR: a test for realistic linked faults. VTS (1996)
Ad J. van de Goor, Aad Offerman, Ivo Schanstra
Towards a Uniform Notation for Memory Tests. ED&TC (1996)
Ad J. van de Goor, Ivo Schanstra, Yervant Zorian
Functional test for shifting-type FIFOs. ED&TC (1995)
Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, Ad J. van de Goor
Coping with Re-usability Using Sequential ATPG: A Practical Case Study. ITC (1995)
M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor
Compact test sets for industrial circuits. VTS (1995)
Mark G. Karpovsky, Ad J. van de Goor, V. N. Yarmolik
Pseudo-exhaustive word-oriented DRAM testing. ED&TC (1995)
Ad J. van de Goor, Yervant Zorian, Ivo Schanstra
Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC (1994)
J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor
Test generation and three-state elements, buses, and bidirectionals. VTS (1994)
Ad J. van de Goor, Yervant Zorian
Effective march algorithms for testing single-order addressed memories. J. Electron. Test. 5 (4) (1994)
Fabian Klass, Michael J. Flynn, Ad J. van de Goor
A 16x16-bit Static CMOS Wave-Pipelined Multiplier. ISCAS (1994)
J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor
Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. ITC (1994)
Fabian Klass, Michael J. Flynn, Ad J. van de Goor
Fast multiplication in VLSI using wave pipelining techniques. J. VLSI Signal Process. 7 (3) (1994)
Yervant Zorian, Ad J. van de Goor, Ivo Schanstra
An Effective BIST Scheme for Ring-Address Type FIFOs. ITC (1994)

Ad J. van de Goor.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Ad J. van de Goor