Jos van Sas

Publication Activity (10 Years)

Years Active: 1989-1996
Publications (10 Years): 0

Publications

Jos van Sas, Urbain Swerts, Marc Darquennes
Test Vector Selection and Application Methodology. ITC (1996)
Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, Ad J. van de Goor
Coping with Re-usability Using Sequential ATPG: A Practical Case Study. ITC (1995)
Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man
Design of a C-testable booth multiplier using a realistic fault model. J. Electron. Test. 5 (1) (1994)
Jos van Sas, Francky Catthoor, Hugo De Man
Cellular automata based deterministic self-test strategies for programmable data paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (7) (1994)
Hans A. R. Manhaeve, Paul L. Wrighton, Jos van Sas, Urbain Swerts
Current Measurement Unit for Telecommunication ASICs. ITC (1994)
Jos van Sas, Geert van Wauwe, Erik Huyskens, Dirk Rabaey
BIST for Embedded Static RAMs with Coverage Calculation. ITC (1993)
Jos van Sas, Francky Catthoor, Hugo De Man
Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories. IEEE Des. Test Comput. 10 (2) (1993)
Jos van Sas, Francky Catthoor, Hugo De Man
Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata. ITC (1992)
Jos van Sas, Francky Catthoor, Peter Vandeput, Frank Rossaert, Hugo De Man
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment. EURO-DAC (1991)
Jos van Sas, Francky Catthoor, Luc Inzé, Hugo De Man
Testability strategy and test pattern generation for register files and customized memories. Microprocess. Microsystems 14 (7) (1990)
Jos van Sas, Francky Catthoor, Hugo De Man
Cellular automata based self-test for programmable data paths. ITC (1990)
Francky Catthoor, Jos van Sas, Luc Inzé, Hugo De Man
A testability strategy for multiprocessor architecture. IEEE Des. Test 6 (2) (1989)