Jörg E. Vollrath

Publication Activity (10 Years)

Years Active: 1997-2018
Publications (10 Years): 1

Top Topics

Graduate Students

Online Learning

Electrical Engineering

Top Venues

Publications

Jörg E. Vollrath
Open Access Microelectronics Course. EWME (2018)
Jörg E. Vollrath
An open access minimum automatic task generation live feedback system for electrical engineering. EDUCON (2015)
Jörg E. Vollrath
Interactive tools for teaching electrical engineering. EDUCON (2014)
Jörg E. Vollrath
Using models, simulation and measurements for teaching circuit design. EDUCON (2013)
Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson
DDR2 DRAM Output Timing Optimization. MTDT (2006)
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath
DRAM-Specific Space of Memory Tests. ITC (2006)
Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. Asian Test Symposium (2005)
Jörg E. Vollrath
Testing and Characterization of SDRAMs. IEEE Des. Test Comput. 20 (1) (2003)
Jörg E. Vollrath
Output Timing Measurement Using an Idd Method. MTDT (2003)
Jörg E. Vollrath
Signal Margin Analysis for Memory Sense Amplifiers . DELTA (2002)
Jörg E. Vollrath, Randall Rooney
Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. ITC (2001)
Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik
Compressed Bit Fail Maps for Memory Fail Pattern Classification. J. Electron. Test. 17 (3-4) (2001)
Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik
Compressed bit fail maps for memory fail pattern classification. ETW (2000)
Jörg E. Vollrath
Synchronous Dynamic Memory Test Construction: A Field Approach. MTDT (2000)
Jörg E. Vollrath
Tutorial: Characterizing SDRAMS. MTDT (1999)
Jörg E. Vollrath, Markus Huebl, Ernst Stahl
Power Analysis of DRAMs. Asian Test Symposium (1998)
Jörg E. Vollrath
Cell Signal Measurement for High-Density DRAMs. ITC (1997)