Ivo Schanstra

Publication Activity (10 Years)

Years Active: 1994-2004
Publications (10 Years): 0

Publications

Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor
Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. MTDT (2004)
Ivo Schanstra, Ad J. van de Goor
Consequences of RAM Bitline Twisting for Test Coverage. DATE (2003)
Ad J. van de Goor, Ivo Schanstra
Address and Data Scrambling: Causes and Impact on Memory Tests. DELTA (2002)
Ad J. van de Goor, Ivo Schanstra
Industrial evaluation of stress combinations for march tests applied to SRAMs. ITC (1999)
Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. ITC (1998)
Ad J. van de Goor, Aad Offerman, Ivo Schanstra
Towards a Uniform Notation for Memory Tests. ED&TC (1996)
Ad J. van de Goor, Ivo Schanstra, Yervant Zorian
Functional test for shifting-type FIFOs. ED&TC (1995)
Ad J. van de Goor, Yervant Zorian, Ivo Schanstra
Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC (1994)
Yervant Zorian, Ad J. van de Goor, Ivo Schanstra
An Effective BIST Scheme for Ring-Address Type FIFOs. ITC (1994)
Ad J. van de Goor, Ivo Schanstra, Yervant Zorian
Fault models and tests for Ring Address Type FIFOs. VTS (1994)