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A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces.

Yoonjae ChoiHyunsu ParkJonghyuck ChoiJincheol SimYoungwook KwonSeungwoo ParkSeongcheol KimChangmin SimChulwoo Kim
Published in: IEEE J. Solid State Circuits (2023)
Keyphrases
  • high speed
  • low power
  • digital images
  • data acquisition
  • motion estimation
  • data structure
  • user interface
  • main memory
  • low complexity
  • memory requirements