A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique.
Soonsung AhnJaegeun SongChaegang LimYohan ChoiSooho ParkYunsoo ParkChulwoo KimPublished in: ISOCC (2020)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- high speed
- synthetic aperture radar
- high power
- logic circuits
- vlsi architecture
- analog to digital converter
- power reduction
- vlsi circuits
- sar images
- low power consumption
- wide dynamic range
- digital signal processing
- cmos technology
- image sensor
- signal processor
- nm technology
- gate array
- video sequences
- cmos image sensor