Hae-Kang Jung

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 9

Top Topics

Mobile Applications

Direct Memory Access

Challenging Sequences

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Taeyang Sim, Sun-Ho Yeom, Hyunwoo Im, Youngmin Oh, Hyeongmin Seo, Hyeongjun Ko, Hankyu Chi, Hae-Kang Jung, Jaeduk Han
A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Yangho Seo, Jihee Choi, Sunki Cho, Hyunwook Han, Wonjong Kim, Gyeongha Ryu, Jungil Ahn, Younga Cho, Sungphil Choi, Seohee Lee, Wooju Lee, Chaehyuk Lee, Kiup Kim, Seongseop Lee, Sangbeom Park, Minjun Choi, Sungwoo Lee, Mino Kim, Taekyun Shin, Hyeongsoo Jeong, Hyunseung Kim, Houk Song, Yunsuk Hong, Seokju Yoon, Giwook Park, Hokeun You, Changkyu Choi, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim
13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction. ISSCC (2024)
Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. IEEE J. Solid State Circuits 58 (8) (2023)
Jihyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. IEEE J. Solid State Circuits 57 (1) (2022)
Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits 56 (6) (2021)
Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Han-Gon Ko, Soyeong Shin, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, Deog-Kyoon Jeong
/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. VLSI Circuits (2019)
Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. IEEE Trans. Circuits Syst. II Express Briefs (2) (2016)
Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi, Young Jae Jang, Hae-Kang Jung, Kyunghoon Kim, Dae-Han Kwon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 51 (8) (2016)
Hae-Kang Jung, Jaemo Yang, Jeonghun Lee, Hyeongjun Ko, Hyuk Lee, Taeksang Song, Jongjoo Shim, Sangkwon Lee, Keunsoo Song, Dongkyun Kim, Hyungsoo Kim, Yunsaing Kim
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications. VLSIC (2015)
Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Yong-Ju Kim, Yunsaing Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 49 (11) (2014)
Hae-Kang Jung, Il-Min Yi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines. IEEE J. Solid State Circuits 47 (9) (2012)
Hae-Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park
A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines. CICC (2010)
Hae-Kang Jung, Kyoungho Lee, Jong-Sam Kim, Jae-Jin Lee, Jae-Yoon Sim, Hong-June Park
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control. IEEE J. Solid State Circuits 44 (11) (2009)