Joo-Hwan Cho

Publication Activity (10 Years)

Years Active: 2002-2022
Publications (10 Years): 3

Top Topics

Uniformly Distributed

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

Publications

Soyeong Shin, Yongjae Lee, Jiheon Park, Jihyo Kang, Kyunghoon Kim, Dae-Han Kwon, Sangkwon Lee, Jieun Jang, Joo-Hwan Cho, Deog-Kyoon Jeong
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Jihyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. IEEE J. Solid State Circuits 57 (1) (2022)
Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. ISSCC (2019)
Dongsuk Shin, Joo-Hwan Cho, Young-Jung Choi, Byong-Tae Chung
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster. SoCC (2010)
Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. IEEE J. Solid State Circuits 42 (11) (2007)
Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo-Hwan Cho, Pil Soo Lee, Jin-Hong Ahn, Jin-Yong Chung
A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM. IEEE J. Solid State Circuits 37 (6) (2002)