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A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay.

Soyeong ShinYongjae LeeJiheon ParkJihyo KangKyunghoon KimDae-Han KwonSangkwon LeeJieun JangJoo-Hwan ChoDeog-Kyoon Jeong
Published in: IEEE Trans. Circuits Syst. II Express Briefs (2022)
Keyphrases
  • power consumption
  • high speed
  • duty cycle
  • clock frequency
  • real time
  • data sets
  • neural network
  • spatial distribution
  • uniformly distributed
  • packet scheduling