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A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.

Ki-Won LeeJoo-Hwan ChoByoung-Jin ChoiGeun-Il LeeHo-Don JungWoo-Young LeeKi-Chon ParkYongsuk JooJaehoon ChaYoung-Jung ChoiPatrick B. MoranJin-Hong Ahn
Published in: IEEE J. Solid State Circuits (2007)
Keyphrases
  • high speed
  • training phase
  • feedback loop
  • frequency modulation
  • signal processing
  • primal dual
  • neural network
  • genetic algorithm
  • objective function
  • motion estimation
  • input data
  • user input
  • circuit design