A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
Jihyo KangJaehyeok YangKyunghoon KimJoo-Hyung ChaeGang-Sik LeeSang-Yeon ByeonBoram KimDong-Hyun KimYoungtaek KimYeongmuk ChoJunghwan JiSera JeongJaehoon ChaMinsoo ParkHongdeuk KimSijun ParkSunho KimHae-Kang JungJieun JangSangkwon LeeHyungsoo KimJoo-Hwan ChoJunhyun ChunSeon-Yong ChaPublished in: IEEE J. Solid State Circuits (2022)