13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction.
Yangho SeoJihee ChoiSunki ChoHyunwook HanWonjong KimGyeongha RyuJungil AhnYounga ChoSungphil ChoiSeohee LeeWooju LeeChaehyuk LeeKiup KimSeongseop LeeSangbeom ParkMinjun ChoiSungwoo LeeMino KimTaekyun ShinHyeongsoo JeongHyunseung KimHouk SongYunsuk HongSeokju YoonGiwook ParkHokeun YouChangkyu ChoiHae-Kang JungJoohwan ChoJonghwan KimPublished in: ISSCC (2024)