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A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique.

Jaegeun SongYunsoo ParkChaegang LimYohan ChoiSoonsung AhnSooho ParkChulwoo Kim
Published in: IEEE J. Solid State Circuits (2022)
Keyphrases
  • error tolerant
  • machine learning
  • data mining
  • pairwise
  • keypoints
  • application domains
  • graph matching
  • subgraph isomorphism