Sanghune Park

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 10

Top Topics

Design Methodologies

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. IEEE J. Solid State Circuits 59 (1) (2024)
Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. ISSCC (2023)
Kihwan Seong, Donguk Park, Gyeom-Je Bae, Hyunwoo Lee, Youngseob Suh, Wooseuk Oh, Hyemun Lee, Juyoung Kim, Takgun Lee, Geonhoo Mo, Sukhyun Jung, Dongcheol Choi, Byoung-Joo Yoo, Sanghune Park, Hyo-Gyuem Rhew, Jongshin Shin
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. ISSCC (2023)
Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin
A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. CICC (2023)
Soo-Min Lee, Kihwan Seong, Joohee Shin, Hyoungjoong Kim, Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyounghoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. ISSCC (2020)
Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. VLSI Circuits (2019)
Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park
Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. ISOCC (2018)
Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Sanghune Park, Chulwoo Kim
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. IEEE Trans. Circuits Syst. II Express Briefs (6) (2018)
Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, SuHo Kim, Sanghune Park, Sanghyun Lee, Sungho Park
23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. ISSCC (2017)
Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee
A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. ESSCIRC (2016)