Wonsik Yu

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 3

Top Topics

Metal Oxide Semiconductor

Analog To Digital Converter

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin
A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. CICC (2023)
Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An, Wonsik Yu, Chanyoung Jeong, WooSeok Kim, Michael Choi, Jongshin Shin
Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application. ISSCC (2022)
Dongin Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho
A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits. IEEE Trans. Circuits Syst. II Express Briefs (10) (2019)
Wonsik Yu, KwangSeok Kim, SeongHwan Cho
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter. IEEE J. Solid State Circuits 50 (5) (2015)
Jungho Kim, Young-Hwa Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs (7) (2015)
KwangSeok Kim, Wonsik Yu, SeongHwan Cho
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. IEEE J. Solid State Circuits 49 (4) (2014)
Wonsik Yu, KwangSeok Kim, SeongHwan Cho
Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2014)
Wonsik Yu, KwangSeok Kim, SeongHwan Cho
A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator. CICC (2013)
Wonsik Yu, Jaewook Kim, KwangSeok Kim, SeongHwan Cho
A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2013)
KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. IEEE J. Solid State Circuits 48 (4) (2013)
KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. VLSIC (2012)
Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. ISSCC (2011)