Clock distribution networks for 3-D ictegrated Circuits.

Vasilis F. Pavlidis Ioannis Savidis Eby G. Friedman

Published in: CICC (2008)

Keyphrases

hit ratio
distribution networks
high speed
lead time
power consumption
analog circuits
duty cycle
delay insensitive
analog vlsi
circuit design
power dissipation
vlsi circuits
power reduction
logic circuits
digital circuits
high level synthesis
tunnel diode
data sets
low power
expert systems
machine learning