Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping.
Yann CivaleDeniz Sabuncuoglu TezcanHarold G. G. PhilipsenP. JaenenRahul AgarwalF. DuvalPhilippe SoussanYoussef TravalyEric BeynePublished in: 3DIC (2009)
Keyphrases
- high speed
- solar cell
- thin film
- si sio
- electron microscopy
- high density
- neural network
- cost effective
- higher level
- computer systems
- data processing
- supply chain
- personal computer
- integrated circuit
- case study
- computer simulation
- multi class
- mobile devices
- parallel computing
- information technology
- massively parallel
- high end
- learning algorithm
- multichip module
- data sets