Piotr Dudek

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 34

Top Topics

Processor Array

Depth From Focus

Gaze Estimation

Approximate Inference

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Piotr Dudek
Factor Machine: Mixed-signal Architecture for Fine-Grained Graph-Based Computing. CoRR (2024)
Laurie Bose, Piotr Dudek
Mapping Image Transformations Onto Pixel Processor Arrays. CoRR (2024)
Haley M. So, Laurie Bose, Piotr Dudek, Gordon Wetzstein
PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors. CoRR (2023)
Laurie Bose, Piotr Dudek, Stephen J. Carey, Jianing Chen
Live Demonstration: SCAMP-7. CVPR Workshops (2023)
Haley M. So, Julien N. P. Martel, Gordon Wetzstein, Piotr Dudek
MantissaCam: Learning Snapshot High-dynamic-range Imaging with Perceptually-based In-pixel Irradiance Encoding. ICCP (2022)
Piotr Dudek, Tom Richardson, Laurie Bose, Stephen J. Carey, Jianing Chen, Colin Greatwood, Yanan Liu, Walterio W. Mayol-Cuevas
Sensor-level computer vision with pixel processor arrays for agile robots. Sci. Robotics 7 (67) (2022)
Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek
Pixel Processor Arrays For Low Latency Gaze Estimation. VR Workshops (2022)
Yanan Liu, Laurie Bose, Yao Lu, Piotr Dudek, Walterio W. Mayol-Cuevas
On-Sensor Binarized Fully Convolutional Neural Network with A Pixel Processor Array. CoRR (2022)
Yanan Liu, Laurie Bose, Colin Greatwood, Jianing Chen, Rui Fan, Thomas Richardson, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
Agile reactive navigation for a non-holonomic mobile robot using a pixel processor array. IET Image Process. 15 (9) (2021)
Yanan Liu, Jianing Chen, Laurie Bose, Piotr Dudek, Walterio W. Mayol-Cuevas
Direct Servo Control from In-Sensor CNN Inference with A Pixel Processor Array. CoRR (2021)
Haley M. So, Julien N. P. Martel, Piotr Dudek, Gordon Wetzstein
MantissaCam: Learning Snapshot High-dynamic-range Imaging with Perceptually-based In-pixel Irradiance Encoding. CoRR (2021)
Yanan Liu, Jianing Chen, Laurie Bose, Piotr Dudek, Walterio W. Mayol-Cuevas
Bringing A Robot Simulator to the SCAMP Vision System. CoRR (2021)
Germain Haessig, Daniel García-Lesta, Gregor Lenz, Ryad Benosman, Piotr Dudek
A Mixed-Signal Spatio-Temporal Signal Classifier for On-Sensor Spike Sorting. ISCAS (2020)
Laurie Bose, Piotr Dudek, Jianing Chen, Stephen J. Carey, Walterio W. Mayol-Cuevas
Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays. ECCV (29) (2020)
Stephen J. Carey, Laurie Bose, Thomas S. Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Piotr Dudek
Live Demonstration: CNN Inference on the Focal Plane with a Pixel Processor Array. ISCAS (2020)
Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek, Gordon Wetzstein
Neural Sensors: Learning Pixel Exposures for HDR Imaging and Video Compressive Sensing With Programmable Sensors. IEEE Trans. Pattern Anal. Mach. Intell. 42 (7) (2020)
Jianing Chen, Yanan Liu, Stephen J. Carey, Piotr Dudek
Proximity Estimation Using Vision Features Computed On Sensor. ICRA (2020)
Tobi Delbrück, Ibrahim Abe M. Elfadel, Shahzad Muzaffar, Germain Haessig, Bo Wang, Amine Bermak, Rui Graca, Luis A. Camuñas-Mesa, Bathiya Senevirathna, Pamela Abshire, Bernabé Linares-Barranco, Saeed Afshar, Shih-Chii Liu, Runchun Mark Wang, Piotr Dudek, Stephen J. Carey, José M. de la Rosa, Marc Dandin, Sheung Lu, Vincent Frick, Teresa Serrano-Gotarredona, Paula López, Melika Payvand, Advait Madhavan, Eric R. Fossum, Juan Camilo Vasquez Tieck, Ian Williams, Yan Liu, Timothy G. Constandinou, Alexander Serb, Ricardo Carmona-Galán, Robert Nawrocki, Walter D. Leon-Salas
Lessons Learned the Hard Way. ISCAS (2020)
Alexander McConville, Laurie Bose, Robert Clarke, Walterio W. Mayol-Cuevas, Jianing Chen, Colin Greatwood, Stephen J. Carey, Piotr Dudek, Thomas Richardson
Visual Odometry Using Pixel Processor Arrays for Unmanned Aerial Systems in GPS Denied Environments. Frontiers Robotics AI 7 (2020)
Yanan Liu, Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
High-speed Light-weight CNN Inference via Strided Convolutions on a Pixel Processor Array. BMVC (2020)
Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays. CoRR (2020)
Yanan Liu, Laurie Bose, Colin Greatwood, Jianing Chen, Rui Fan, Thomas S. Richardson, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
Agile Reactive Navigation for A Non-Holonomic Mobile Robot Using A Pixel Processor Array. CoRR (2020)
Laurie Bose, Piotr Dudek, Jianing Chen, Stephen J. Carey, Walterio W. Mayol-Cuevas
A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays. ICCV (2019)
Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays. CoRR (2019)
Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
Live Demonstration: Digit Recognition on Pixel Processor Arrays. CVPR Workshops (2019)
Jianing Chen, Stephen J. Carey, Piotr Dudek
Scamp5d Vision System and Development Framework. ICDSC (2018)
Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Jonathan Müller, Yulia Sandamirskaya, Piotr Dudek
Real-Time Depth From Focus on a Programmable Focal Plane Processor. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2018)
Colin Greatwood, Laurie Bose, Thomas Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Stephen J. Carey, Piotr Dudek
Perspective Correcting Visual Odometry for Agile MAVs using a Pixel Processor Array. IROS (2018)
Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Jonathan Müller, Yulia Sandamirskaya, Piotr Dudek
Live demonstration: Depth from focus on a focal plane processor using a focus tunable liquid lens. ISCAS (2017)
Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas
Visual Odometry for Pixel Processor Arrays. ICCV (2017)
Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek
High-speed depth from focus on a programmable vision chip using a focus tunable lens. ISCAS (2017)
Colin Greatwood, Laurie Bose, Thomas S. Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Stephen J. Carey, Piotr Dudek
Tracking control of a UAV with a parallel visual processor. IROS (2017)
Julien N. P. Martel, Yulia Sandamirskaya, Piotr Dudek
A Demonstration of Tracking using Dynamic Neural Fields on a Programmable Vision Chip: Demo. ICDSC (2016)
Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek
Parallel HDR tone mapping and auto-focus on a cellular processor array vision chip. ISCAS (2016)
Declan Walsh, Piotr Dudek
An event-driven massively parallel fine-grained processor array. ISCAS (2015)
Julien N. P. Martel, Miguel Chau, Piotr Dudek, Matthew Cook
Toward joint approximate inference of visual quantities on cellular processor arrays. ISCAS (2015)
Julien N. P. Martel, Miguel Chau, Matthew Cook, Piotr Dudek
Pixel interlacing to trade off the resolution of a cellular processor array against more registers. ECCTD (2015)
Manu V. Nair, Piotr Dudek
Gradient-descent-based learning in memristive crossbar arrays. IJCNN (2015)
Przemyslaw Mroszczyk, Piotr Dudek
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Przemyslaw Mroszczyk, Piotr Dudek
Tunable CMOS Delay Gate With Improved Matching Properties. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek
Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision. ISCAS (2014)
Stephen J. Carey, Ákos Zarándy, Piotr Dudek
Characterization of processing errors on analog fully-programmable cellular sensor-processor arrays. ISCAS (2014)
Bin Wang, Piotr Dudek
A Fast Self-Tuning Background Subtraction Algorithm. CVPR Workshops (2014)
Przemyslaw Mroszczyk, Piotr Dudek
The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits. ISCAS (2014)
David Robert Wallace Barr, Declan Walsh, Piotr Dudek
A Smart Surface Simulation Environment. SMC (2013)
Przemyslaw Mroszczyk, Piotr Dudek
Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays. ECCTD (2013)
Bin Wang, Piotr Dudek
AMBER: Adapting multi-resolution background extractor. ICIP (2013)
Stephen J. Carey, David Robert Wallace Barr, Piotr Dudek
Low power high-performance smart camera system based on SCAMP vision sensor. J. Syst. Archit. 59 (10-A) (2013)
Alexey Lopich, Piotr Dudek
A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array. CICC (2013)
Przemyslaw Mroszczyk, Piotr Dudek
Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters. NEWCAS (2013)
Ioannis Georgilas, Andrew Adamatzky, David Robert Wallace Barr, Piotr Dudek, Chris Melhuish
Metachronal Waves in Cellular Automata: Cilia-Like Manipulation in Actuator Arrays. NICSO (2013)
Declan Walsh, Piotr Dudek
A field programmable array core for image processing (abstract only). FPGA (2012)
Jayawan H. B. Wijekoon, Piotr Dudek
Heterogeneous neurons and plastic synapses in a reconfigurable cortical neural network IC. ISCAS (2012)
Przemyslaw Mroszczyk, Piotr Dudek
Trigger-wave collision detecting asynchronous cellular logic array for fast image skeletonization. ISCAS (2012)
Tao Zhou, Piotr Dudek, Bertram E. Shi
Development of robot self-identification based on visuomotor prediction. ICDL-EPIROB (2012)
Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek
Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps. ICECS (2012)
Jayawan H. B. Wijekoon, Piotr Dudek
Analogue CMOS circuit implementation of a dopamine modulated synapse. ISCAS (2011)
Stephen J. Carey, Alexey Lopich, Piotr Dudek
A processor element for a mixed signal cellular processor array vision chip. ISCAS (2011)
Alexey Lopich, Piotr Dudek
A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2011)
Pamela Abshire, Amine Bermak, Raphael Berner, Gert Cauwenberghs, Shoushun Chen, Jennifer Blain Christen, Timothy G. Constandinou, Eugenio Culurciello, Marc Dandin, Timir Datta, Tobi Delbrück, Piotr Dudek, Amir Eftekhar, Ralph Etienne-Cummings, Giacomo Indiveri, Matthew K. Law, Bernabé Linares-Barranco, Jonathan Tapson, Wei Tang, Yiming Zhai
Confession session: Learning from others mistakes. ISCAS (2011)
Stephen J. Carey, David Robert Wallace Barr, Piotr Dudek
Demonstration of a low power image processing system using a SCAMP3 vision chip. ICDSC (2011)
Alexey Lopich, David Robert Wallace Barr, Bin Wang, Piotr Dudek
Live demonstration: Real-time image processing on ASPA2 vision system. ISCAS (2011)
Alexey Lopich, Piotr Dudek
Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. Int. J. Circuit Theory Appl. 39 (9) (2011)
Alexey Lopich, Piotr Dudek
Architecture and design of a programmable 3D-integrated cellular processor array for image processing. VLSI-SoC (2011)
Tao Zhou, Piotr Dudek, Bertram E. Shi
Self-Organizing Neural Population Coding for improving robotic visuomotor coordination. IJCNN (2011)
Kevin Brohan, Kevin N. Gurney, Piotr Dudek
Using Reinforcement Learning to Guide the Development of Self-organised Feature Maps for Visual Orienting. ICANN (2) (2010)
Alexey Lopich, Piotr Dudek
An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology. ISCAS (2010)
Piotr Dudek, Alexey Lopich, Viktor Gruev
A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology. ECCTD (2009)
David Robert Wallace Barr, Piotr Dudek
APRON: A Cellular Processor Array Simulation and Hardware Design Tool. EURASIP J. Adv. Signal Process. 2009 (2009)
Alexey Lopich, Piotr Dudek
Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing. J. Signal Process. Syst. 56 (1) (2009)
Alexey Lopich, Piotr Dudek
ASPA: Focal Plane digital processor array with asynchronous processing capabilities. ISCAS (2008)
Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaid
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. FPL (2008)
David López Vilariño, Piotr Dudek, Diego Cabello
Focal-plane moving object segmentation for realtime video surveillance. ISCAS (2008)
Jayawan H. B. Wijekoon, Piotr Dudek
Integrated circuit implementation of a cortical neuron. ISCAS (2008)
Carmen Alonso-Montes, David López Vilariño, Piotr Dudek, Manuel G. Penedo
Fast retinal vessel tree extraction: A pixel parallel approach. Int. J. Circuit Theory Appl. 36 (5-6) (2008)
Jayawan H. B. Wijekoon, Piotr Dudek
Compact silicon neuron circuit with spiking and bursting behaviour. Neural Networks 21 (2-3) (2008)
Martin Hülse, David Robert Wallace Barr, Piotr Dudek
Cellular automata and non-static image processing for embodied robot systems on a massively parallel processor array. Automata (2008)
David López Vilariño, Piotr Dudek
Evolution of Pixel Level Snakes towards an efficient hardware implementation. ISCAS (2007)
Jayawan H. B. Wijekoon, Piotr Dudek
Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit. IJCNN (2007)
David Robert Wallace Barr, Piotr Dudek, Jonathan M. Chambers, Kevin N. Gurney
Implementation of multi-layer leaky integrator networks on a cellular processor array. IJCNN (2007)
Alexey Lopich, Piotr Dudek
Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. ECCTD (2007)
Carmen Alonso-Montes, Piotr Dudek, David López Vilariño, Manuel G. Penedo
On chip implementation of a pixel-parallel approach for retinal vessel tree extraction. ECCTD (2007)
Alexey Lopich, Piotr Dudek
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing. ISCAS (2006)
Jayawan H. B. Wijekoon, Piotr Dudek
Simple Analogue VLSI Circuit of a Cortical Neuron. ICECS (2006)
Piotr Dudek
An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays. IEEE Trans. Circuits Syst. II Express Briefs (5) (2006)
Piotr Dudek, V. D. Juncu
An area and power efficient discrete-time chaos generator circuit. ECCTD (2005)
Piotr Dudek
Implementation of SIMD vision chip with 128×128 array of analogue processing elements. ISCAS (6) (2005)
Aliaksei Lopich, Piotr Dudek
Architecture of asynchronous cellular processor array for image skeletonization. ECCTD (2005)
Piotr Dudek, Peter J. Hicks
A general-purpose processor-per-pixel analog SIMD vision chip. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2005)
Piotr Dudek
A 39×48 general-purpose focal-plane processor array integrated circuit. ISCAS (5) (2004)
Piotr Dudek
A flexible global readout architecture for an analogue SIMD vision chip. ISCAS (3) (2003)
Piotr Dudek, Peter J. Hicks
An analogue SIMD focal-plane processor array. ISCAS (4) (2001)
Piotr Dudek, Peter J. Hicks
A CMOS general-purpose sampled-data analogue microprocessor. ISCAS (2000)
Piotr Dudek, Stanislaw Szczepanski, John V. Hatfield
A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE J. Solid State Circuits 35 (2) (2000)