Implementation of SIMD vision chip with 128×128 array of analogue processing elements.
Piotr DudekPublished in: ISCAS (6) (2005)
Keyphrases
- processing elements
- single instruction multiple data
- linear array
- parallel computers
- massively parallel
- reconfigurable hardware
- processor array
- content addressable memory
- hardware implementation
- hardware architecture
- parallel implementation
- parallel architecture
- real time
- parallel architectures
- image processing algorithms
- functional units
- parallel processing
- low cost
- parallel processors
- computer architecture
- computer vision
- associative memory
- random access
- image processing
- neural network
- data transfer
- orders of magnitude
- distributed systems
- lower bound
- pattern recognition
- parallel computing
- parallel algorithm
- high speed