Alexey Lopich

Publication Activity (10 Years)

Years Active: 2006-2014
Publications (10 Years): 0

Top Topics

Integrated Circuit

Processor Array

Top Venues

Publications

Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek
Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision. ISCAS (2014)
Alexey Lopich, Piotr Dudek
A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array. CICC (2013)
Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek
Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps. ICECS (2012)
Stephen J. Carey, Alexey Lopich, Piotr Dudek
A processor element for a mixed signal cellular processor array vision chip. ISCAS (2011)
Alexey Lopich, Piotr Dudek
A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2011)
Alexey Lopich, David Robert Wallace Barr, Bin Wang, Piotr Dudek
Live demonstration: Real-time image processing on ASPA2 vision system. ISCAS (2011)
Alexey Lopich, Piotr Dudek
Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. Int. J. Circuit Theory Appl. 39 (9) (2011)
Alexey Lopich, Piotr Dudek
Architecture and design of a programmable 3D-integrated cellular processor array for image processing. VLSI-SoC (2011)
Alexey Lopich, Piotr Dudek
An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology. ISCAS (2010)
Piotr Dudek, Alexey Lopich, Viktor Gruev
A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology. ECCTD (2009)
Alexey Lopich, Piotr Dudek
Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing. J. Signal Process. Syst. 56 (1) (2009)
Alexey Lopich, Piotr Dudek
ASPA: Focal Plane digital processor array with asynchronous processing capabilities. ISCAS (2008)
Alexey Lopich, Piotr Dudek
Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. ECCTD (2007)
Alexey Lopich, Piotr Dudek
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing. ISCAS (2006)