Snorre Aunet

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 22

Top Topics

Comparative Analysis

Cmos Technology

Selected Papers

Top Venues

Microprocess. Microsystems

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Jari Nurmi, Snorre Aunet, Alireza Saberkari
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022. IEEE Trans. Very Large Scale Integr. Syst. 32 (1) (2024)
Magnus Amble, Snorre Aunet, Dag T. Wisland, Kristian Gjertsen Kjelgård
Randomized Bulk-Voltages: A Countermeasure to Mask Side-Channel Leakage of CMOS Logic Gates. MWSCAS (2023)
Azam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg
Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements. IEEE Access 10 (2022)
Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. NorCAS (2021)
Yahya H. Yassin, Magnus Jahre, Per Gunnar Kjeldsberg, Snorre Aunet, Francky Catthoor
Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode. J. Signal Process. Syst. 93 (1) (2021)
Snorre Aunet
Ultra Low Voltage Sub-100 mV Vdd CMOS. NEWCAS (2021)
Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology. NorCAS (2020)
Even Låte, Trond Ytterdal, Snorre Aunet
An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V. IEEE Trans. Circuits Syst. (11) (2020)
Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders. NorCAS (2020)
Even Låte, Trond Ytterdal, Snorre Aunet
Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. IEEE Trans. Very Large Scale Integr. Syst. 28 (10) (2020)
Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. NORCAS (2019)
Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. NORCAS (2019)
Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI. IEEE Trans. Circuits Syst. II Express Briefs (6) (2019)
Steinar Thune Christensen, Snorre Aunet, Omer Qadir
A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks. NORCAS (2019)
Azam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg
Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications. NORCAS (2019)
Even Låte, Trond Ytterdal, Snorre Aunet
A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology. Integr. 63 (2018)
Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology. NORCAS (2018)
Ali Asghar Vatanjou, Even Låte, Trond Ytterdal, Snorre Aunet
Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing. Microprocess. Microsystems 56 (2018)
Even Låte, Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocess. Microsystems 48 (2017)
Jim Tørresen, Snorre Aunet
Special issue: Selected papers from the 1st NORCAS conference (2015 Nordic Circuits and Systems Conference (NORCAS): Norchip & International Symposium on System-on-Chip (SoC)). Microprocess. Microsystems 48 (2017)
Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block. MIXDES (2016)
Ali Asghar Vatanjou, Even Låte, Trond Ytterdal, Snorre Aunet
Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing. NORCAS (2016)
Even Låte, Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI. NORCAS (2015)
Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
4 Sub-/near-threshold flip-flops with application to frequency dividers. ECCTD (2015)
Hourieh Attarzadeh, Snorre Aunet, Trond Ytterdal
An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm. NORCAS (2015)
Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
Exploiting short channel effects and multi-Vt technology for increased robustness and reduced energy consumption, with application to a 16-bit subthreshold adder implemented in 65 nm CMOS. ECCTD (2015)
Jonathan Edvard Bjerkedok, Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
Modular layout-friendly cell library design applied for subthreshold CMOS. NORCHIP (2014)
Magne Voernes, Trond Ytterdal, Snorre Aunet
Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout. NORCHIP (2014)
Amir Hasanbegovic, Snorre Aunet
Proton beam characterization at Oslo Cyclotron Laboratory for radiation testing of electronic devices. DDECS (2013)
Hans Kristian Otnes Berge, Snorre Aunet
Yield-oriented energy and performance model for subthreshold circuits with Vth variations. DDECS (2013)
Sven Lütkemeier, Thorsten Jungeblut, Hans Kristian Otnes Berge, Snorre Aunet, Mario Porrmann, Ulrich Rückert
A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control. IEEE J. Solid State Circuits 48 (1) (2013)
Tuan Vu Cao, Snorre Aunet, Trond Ytterdal
A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS. NORCHIP (2012)
Amir Hasanbegovic, Snorre Aunet
Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process. Microprocess. Microsystems 35 (1) (2011)
Hans Kristian Otnes Berge, Snorre Aunet
Multi-objective optimization of minority-3 functions for ultra-low voltage supplies. ISCAS (2011)
Snorre Aunet
On the reliability of ultra low voltage circuits built from minority-3 gates. ECCTD (2011)
Hans Kristian Otnes Berge, Amir Hasanbegovic, Snorre Aunet
Muller C-elements based on minority-3 functions for ultra low voltage supplies. DDECS (2011)
Hans Kristian Otnes Berge, Matthias W. Blesken, Snorre Aunet, Ulrich Rückert
Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach. ICECS (2010)
Snorre Aunet, Amir Hasanbegovic
Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS. DDECS (2010)
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Snorre Aunet, Tuan Vu Cao, Ali Peiravi
Ultra Low Power Full Adder Topologies. ISCAS (2009)
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao
New subthreshold concepts in 65nm CMOS technology. ISQED (2009)
Yngvar Berg, Omid Mirmotahari, Snorre Aunet
Clocked semi-floating-gate ultra low-voltage current mirror. ICECS (2008)
Snorre Aunet, Bengt Oelmann, Per Andreas Norseng, Yngvar Berg
Real-Time Reconfigurable Subthreshold CMOS Perceptron. IEEE Trans. Neural Networks 19 (4) (2008)
Kristian Granhaug, Snorre Aunet
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. J. Electron. Test. 24 (1-3) (2008)
Håvard Pedersen Alstad, Snorre Aunet
Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation. DDECS (2008)
Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao
65NM sub-threshold 11T-SRAM for ultra low voltage applications. SoCC (2008)
Yngvar Berg, Omid Mirmotahari, Snorre Aunet
Ultra low voltage and, nor and XOR CMOS gates. ICECS (2008)
Håvard Pedersen Alstad, Snorre Aunet
Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology. DDECS (2008)
Yngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet
High Speed Ultra Low Voltage CMOS inverter. ISVLSI (2008)
Yngvar Berg, Omid Mirmotahari, Snorre Aunet
High speed and ultra low voltage CMOS latch. ICECS (2008)
Jon Alfredsson, Snorre Aunet
Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. PATMOS (2007)
Yngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet
Fault Tolerant CMOS Logic Using Ternary Gates. ISMVL (2007)
Snorre Aunet, Hans Kristian Otnes Berge
Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits. IWANN (2007)
Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Walid Ibrahim
Serial Addition: Locally Connected Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2007)
Yngvar Berg, Mehdi Azadmehr, Omid Mirmotahari, Snorre Aunet
Band Pass Pseudo Floating-Gate Amplifier. ICECS (2007)
Jon Alfredsson, Snorre Aunet, Bengt Oelmann
Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure. VLSI Design (2007)
Kristian Granhaug, Snorre Aunet
Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. DFT (2006)
Yngvar Berg, Omid Mirmotahari, Per Andreas Norseng, Snorre Aunet
Ultra low voltage CMOS gates. ICECS (2006)
Kristian Granhaug, Snorre Aunet, Tor Sverre Lande
Body-bias regulator for ultra low power multifunction CMOS gates. ISCAS (2006)
Yngvar Berg, Omid Mirmotahari, Snorre Aunet
Pseudo Floating-Gate Inverter with Feedback Control. VLSI-SoC (2006)
Kristian Granhaug, Snorre Aunet
Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology. DDECS (2006)
Valeriu Beiu, Jabulani Nyathi, Snorre Aunet, Mawahib H. Sulieman
Femto Joule Switching for Nano Electronics. AICCSA (2006)
Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet
Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. IWANN (2005)
Valeriu Beiu, Artur Zawadski, Razvan Andonie, Snorre Aunet
Using Kolmogorov Inspired Gates for Low Power Nanoelectronics. IWANN (2005)
Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal
On the Advantages of Serial Architectures for Low-Power Reliable Computations. ASAP (2005)
Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari
Basic Multiple-Valued Functions Using Recharge CMOS Logic. ISMVL (2004)
Snorre Aunet, Yngvar Berg, Trond Sæther
Erratum to "real-time reconfigurable linear threshold elements implemented in floating-gate CMOS". IEEE Trans. Neural Networks 14 (6) (2003)
Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin
Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. ISCAS (1) (2003)
Snorre Aunet, Morten Hartmann
Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware. ICES (2003)
Yngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin
Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. ISCAS (5) (2003)
Snorre Aunet, Yngvar Berg, Trond Sæther
Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS. IEEE Trans. Neural Networks 14 (5) (2003)
Snorre Aunet, Yngvar Berg
UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3". IWANN (2) (2003)
Yngvar Berg, Øivind Næss, Snorre Aunet, Mats Høvin
A novel floating-gate multiple-valued signal to binary signal converter. ICECS (2002)
Yngvar Berg, Øivind Næss, Snorre Aunet, Johannes Goplen Lomsdalen, Mats Høvin
A novel floating-gate binary signal to multiple-valued signal converter for multiple-valued CMOS logic. ICECS (2002)
Yngvar Berg, Øivind Næss, Snorre Aunet, Renè Jensen, Mats Høvin
Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. ISCAS (5) (2002)
Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin
A novel floating-gate multiple-valued CMOS full-adder. ISCAS (1) (2002)
Trond Ytterdal, Snorre Aunet
Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. ISCAS (5) (2002)
Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
A novel low-voltage floating-gate CMOS transconductance amplifier with sinh (tanh) shaped output current. ICECS (2001)
Snorre Aunet, Yngvar Berg, Trond Ytterdal, Øivind Næss, Trond Sæther
A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits. ICECS (2001)
Snorre Aunet, Yngvar Berg, Øivind Næss, Trond Sæther
Novel reconfigurable two-MOSFET UV-programmable floating-gate circuits for CARRY, NAND, NOR or INVERT functions. ICECS (2001)
Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
Floating-gate CMOS differential analog inverter for ultra low-voltage applications. ISCAS (1) (2001)
Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin
Extreme low-voltage floating-gate CMOS transconductance amplifier. ISCAS (1) (2001)
Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. ISCAS (4) (2001)
Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin
A 0.3 V floating-gate differential amplifier input stage with tunable gain. ICECS (2001)