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Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS.

Snorre AunetAmir Hasanbegovic
Published in: DDECS (2010)
Keyphrases
  • high speed
  • low cost
  • cmos technology
  • memory usage
  • data sets
  • neural network
  • image processing
  • power consumption
  • low power
  • random access
  • memory space
  • circuit design
  • logic circuits
  • delay insensitive
  • silicon on insulator