Randomized Bulk-Voltages: A Countermeasure to Mask Side-Channel Leakage of CMOS Logic Gates.
Magnus AmbleSnorre AunetDag T. WislandKristian Gjertsen KjelgårdPublished in: MWSCAS (2023)
Keyphrases
- countermeasures
- logic circuits
- delay insensitive
- power analysis
- low power
- high speed
- random access memory
- information security
- chip design
- multi valued
- modal logic
- asynchronous circuits
- low cost
- smart card
- power consumption
- analog vlsi
- proof theory
- information systems
- floating gate
- power dissipation
- classical logic
- logic programming
- real time
- electric field
- power supply
- transmission line
- model checking