Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology.

Håvard Pedersen Alstad Snorre Aunet

Published in: DDECS (2008)

Keyphrases

cmos technology
low voltage
low power
flip flops
power dissipation
spl times
power consumption
parallel processing
silicon on insulator
high speed
low cost
image sensor
random access memory
object oriented
pattern recognition
case study
real time