Login / Signup
Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits.
Snorre Aunet
Hans Kristian Otnes Berge
Published in:
IWANN (2007)
Keyphrases
</>
power consumption
power reduction
clock gating
power dissipation
low power
power management
energy efficiency
power saving
low voltage
cmos technology
random access memory
energy saving
data center
high speed
battery life
battery powered
energy management
nm technology
power control