A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks.
Steinar Thune ChristensenSnorre AunetOmer QadirPublished in: NORCAS (2019)
Keyphrases
- low power
- energy efficient
- vlsi architecture
- low cost
- power consumption
- convolutional neural networks
- energy efficiency
- single chip
- wireless sensor networks
- high speed
- energy consumption
- signal processor
- sensor networks
- mixed signal
- digital signal processing
- real time
- low power consumption
- vlsi implementation
- image sensor
- multi hop
- cmos technology
- hardware architecture
- nm technology
- power management
- base station
- hardware and software
- hardware implementation
- routing protocol
- data transmission
- logic circuits
- computer systems
- gate array
- embedded systems
- data center
- data streams