Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology.
Somayeh Hossein ZadehTrond YtterdalSnorre AunetPublished in: NORCAS (2019)
Keyphrases
- cmos technology
- low voltage
- digital circuits
- low power
- mixed signal
- high speed
- power consumption
- parallel processing
- power line
- silicon on insulator
- reactive power
- image sensor
- data flow
- low cost
- random access memory
- circuit design
- power dissipation
- design considerations
- leakage current
- digital signal processing
- optimal solution
- real time
- finite state machines
- cost effective