A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology.

Even Låte Trond Ytterdal Snorre Aunet

Published in: Integr. (2018)

Keyphrases

cmos technology
silicon on insulator
low power
power consumption
spl times
low voltage
parallel processing
power dissipation
dynamic random access memory
image sensor
high speed
mixed signal
power management
low cost
embedded dram
digital signal processing
design process
ibm power processor
image processing
real time