Liesbeth Witters

Publication Activity (10 Years)

Years Active: 2009-2018
Publications (10 Years): 3

Top Topics

Silicon Dioxide

Technical Challenges

Electrical Properties

Top Venues

Microelectron. Reliab.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

A. Vandooren, Liesbeth Witters, Jacopo Franco, Arindam Mallik, Bertrand Parvais, Z. Wu, Amey Walke, V. Deshpande, E. Rosseel, Andriy Hikavyy, W. Li, L. Peng, Nouredine Rassoul, Geraldine Jamieson, Fumihiro Inoue, G. Verbinnen, Katia Devriendt, Lieve Teugels, N. Heylen, E. Vecchio, T. Zheng, Niamh Waldron, Vincent De Heyn, Dan Mocuta, Nadine Collaert
Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling. ICICDT (2018)
Shimpei Yamaguchi, Liesbeth Witters, Jérôme Mitard, Geert Eneman, Geert Hellings, Andriy Hikavyy, Roger Loo, Naoto Horiguchi
implant free quantum well pFET. Microelectron. Reliab. 83 (2018)
Nadine Collaert, AliReza Alian, H. Arimura, Geert Boccardi, Geert Eneman, Jacopo Franco, Tsvetan Ivanov, Dennis Lin, Jérôme Mitard, S. Ramesh, R. Rooyackers, Marc Schaekers, A. Sibaya-Hernandez, S. Sioncke, Quentin Smets, Abhitosh Vais, A. Vandooren, Anabela Veloso, Anne S. Verhulst, D. Verreck, Niamh Waldron, Amey Walke, Liesbeth Witters, H. Yu, X. Zhou, Aaron Voon-Yew Thean
Beyond-Si materials and devices for more Moore and more than Moore applications. ICICDT (2016)
Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jérôme Mitard, Liesbeth Witters, Thomas Y. Hoffmann
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Jacopo Franco, Ben Kaczer, Jérôme Mitard, Maria Toledano-Luque, Felice Crupi, Geert Eneman, Ph. J. Rousse, Tibor Grasser, M. Cho, Thomas Kauerauf, Liesbeth Witters, Geert Hellings, L.-Å. Ragnarsson, Naoto Horiguchi, Marc M. Heyns, Guido Groeseneken
Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. ICICDT (2012)
Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jérôme Mitard, Liesbeth Witters, Thomas Y. Hoffmann
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. ISCAS (2011)
Thomas Chiarella, Liesbeth Witters, Abdelkarim Mercha, Christoph Kerner, Rok Dittrich, Michal Rakowski, Claude Ortolland, Lars-Åke Ragnarsson, Bertrand Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, Philippe Absil, S. Biesemans, Thomas Y. Hoffmann
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? ESSCIRC (2009)