Robert Gauthier

Publication Activity (10 Years)

Years Active: 2003-2021
Publications (10 Years): 6

Top Topics

Cmos Technology

Gallium Arsenide

Charge Coupled Device

Top Venues

Publications

Sagar Premnath Karalkar, Vishal Ganesan, Milova Paul, Kyong Jin Hwang, Robert Gauthier
Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp. IRPS (2021)
You Li, Meng Miao, Robert Gauthier
ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies. CICC (2020)
Kyong Jin Hwang, Sagar Premnath Karalkar, Vishal Ganesan, Sevashanmugam Marimuthu, Alban Zaka, Tom Herrmann, Bhoopendra Singh, Robert Gauthier
Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology. IRPS (2020)
Zhiqing Li, Baofu Zhu, Anindya Nath, Meng Miao, Alain Loiseau, You Li, Jeffrey B. Johnson, Souvick Mitra, Robert Gauthier
Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation. IRPS (2020)
Jie Jack Zeng, Ruchil Jain, Kyong Jin Hwang, Robert Gauthier
A Novel HV-NPN ESD Protection Device with Buried Floating P-Type Implant. IRPS (2019)
Ahmed Y. Ginawi, Robert Gauthier, Tian Xia
Investigation of diode triggered silicon control rectifier turn-on time during ESD events. SoCC (2017)
Ahmed Ginawi, Tian Xia, Robert Gauthier
Reducing the turn-on time and overshoot voltage for a diode-triggered silicon-controlled rectifier during an electrostatic discharge event. SoCC (2014)
Judi McCuaig, Robert Gauthier
Interoperability for ITS: An Ontology of Learning Style Models. ITS (2012)
Ali Khaki-Firooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam Shahidi
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. ISSCC (2010)
Tommaso Cilento, M. Schenkel, C. Yun, R. Mishra, Junjun Li, Kiran V. Chatty, Robert Gauthier
Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology. Microelectron. Reliab. 50 (9-11) (2010)
Adrien Ille, Wolfgang Stadler, Thomas Pompl, Harald Gossner, Tilo Brodbeck, Kai Esmark, Philipp Riess, David Alvarez, Kiran V. Chatty, Robert Gauthier, Alain Bravaix
Reliability aspects of gate oxide under ESD pulse stress. Microelectron. Reliab. 49 (12) (2009)
David Alvarez, Kiran V. Chatty, Christian Russ, Michel J. Abou-Khalil, Junjun Li, Robert Gauthier, Kai Esmark, Ralph Halbach, Christopher Seguin
Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology. Microelectron. Reliab. 49 (12) (2009)
Ciaran J. Brennan, Shunhua Chang, Min Woo, Kiran V. Chatty, Robert Gauthier
Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs. Microelectron. Reliab. 47 (7) (2007)
Ciaran J. Brennan, Kiran V. Chatty, Jeff Sloan, Paul Dunn, Mujahid Muhammad, Robert Gauthier
Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs. Microelectron. Reliab. 47 (7) (2007)
David Alvarez, Michel J. Abou-Khalil, Christian Russ, Kiran V. Chatty, Robert Gauthier, D. Kontos, Junjun Li, Christopher Seguin, Ralph Halbach
Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant. Microelectron. Reliab. 46 (9-11) (2006)
Franco Stellari, Peilin Song, Moyra K. McManus, Alan J. Weger, Robert Gauthier, Kiran V. Chatty, Mujahid Muhammad, Pia Sanda, Philip Wu, Steve Wilson
Latchup Analysis Using Emission Microscopy. Microelectron. Reliab. 43 (9-11) (2003)
Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia Sanda
Optical and Electrical Testing of Latchup in I/O Interface Circuits. ITC (2003)