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Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp.
Sagar Premnath Karalkar
Vishal Ganesan
Milova Paul
Kyong Jin Hwang
Robert Gauthier
Published in:
IRPS (2021)
Keyphrases
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cmos technology
low voltage
power consumption
low power
power dissipation
silicon on insulator
spl times
low cost
image processing
parallel processing
power system
power losses
motion vectors
single phase
object oriented
random access memory
computer vision