Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology.
David AlvarezKiran V. ChattyChristian RussMichel J. Abou-KhalilJunjun LiRobert GauthierKai EsmarkRalph HalbachChristopher SeguinPublished in: Microelectron. Reliab. (2009)