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Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology.
Kyong Jin Hwang
Sagar Premnath Karalkar
Vishal Ganesan
Sevashanmugam Marimuthu
Alban Zaka
Tom Herrmann
Bhoopendra Singh
Robert Gauthier
Published in:
IRPS (2020)
Keyphrases
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cmos technology
low power
spl times
power consumption
parallel processing
low voltage
silicon on insulator
low cost
power dissipation
motion vectors
mixed signal
high speed
dynamic logic
image sensor
optical flow
multimedia
image processing