Kwen-Siong Chong

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 44

Top Topics

Countermeasures

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Juncheng Chen, Han Zhang, Zishuo Yang, Yicheng Xu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix. ISCAS (2024)
Jun-Sheng Ng, Juncheng Chen, Si Wu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. ISCAS (2023)
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph Chang, Bah-Hwee Gwee
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. ISCAS (2022)
Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. IEEE Trans. Very Large Scale Integr. Syst. 30 (9) (2022)
Jipeng Wang, Zixuan Peng, Yi Zhan, Yujie Li, Guoyi Yu, Kwen-Siong Chong, Chao Wang
A High-Accuracy and Energy-Efficient CORDIC Based Izhikevich Neuron With Error Suppression and Compensation. IEEE Trans. Biomed. Circuits Syst. 16 (5) (2022)
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
Non-profiling based Correlation Optimization Deep Learning Analysis. ISCAS (2022)
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Zhili Zou, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
Incremental Linear Regression Attack. AsianHOST (2022)
Xvpeng Zhang, Bingqiang Liu, Yaqi Zhao, Xiaoyu Hu, Zixuan Shen, Zhaoxia Zheng, Zhenglin Liu, Kwen-Siong Chong, Guoyi Yu, Chao Wang, Xuecheng Zou
Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices. Sensors 22 (23) (2022)
Zixuan Peng, Jipeng Wang, Yi Zhan, Run Min, Guoyi Yu, Jianwen Luo, Kwen-Siong Chong, Chao Wang
A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron. NEWCAS (2021)
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
Normalized Differential Power Analysis - for Ghost Peaks Mitigation. ISCAS (2021)
Jiajun Wu, Xuan Huang, Le Yang, Jipeng Wang, Bingqiang Liu, Ziyuan Wen, Juhui Li, Guoyi Yu, Kwen-Siong Chong, Chao Wang
An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (4) (2021)
Kwen-Siong Chong, Jun-Sheng Ng, Juncheng Chen, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Joseph Sylvester Chang, Bah-Hwee Gwee
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (2) (2021)
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection. IEEE Trans. Circuits Syst. II Express Briefs 68 (6) (2021)
Juncheng Chen, Jun-Sheng Ng, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Weng-Geng Ho, Ali Akbar Pammu, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications. ISOCC (2020)
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). ISCAS (2020)
Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. ISCAS (2020)
Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. APCCAS (2020)
Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller. ISCAS (2020)
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
A Secure Data-Toggling SRAM for Confidential Data Protection. ISCAS (2020)
Jiajun Wu, Xuan Huang, Le Yang, Liang Wang, Jipeng Wang, Zuozhu Liu, Kwen-Siong Chong, Shaowei Lin, Chao Wang
An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity. A-SSCC (2020)
Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, W. Shu, Joseph S. Chang, Bah-Hwee Gwee
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. ISCAS (2019)
Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. AsianHOST (2019)
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
A Secure Data-Toggling SRAM for Confidential Data Protection. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2019)
Ali Akbar Pammu, Kwen-Siong Chong, Yi Wang, Bah-Hwee Gwee
A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information. IEEE Trans. Dependable Secur. Comput. 16 (3) (2019)
Ali Akbar Pammu, Weng-Geng Ho, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor. IEEE Trans. Inf. Forensics Secur. 14 (4) (2019)
Weng-Geng Ho, Ali Akbar Pammu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications. SoCC (2019)
Wei Shu, Jize Jiang, Kwen-Siong Chong, Joseph Sylvester Chang
Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things. DSL (2018)
Weng-Geng Ho, Zixian Zheng, Kwen-Siong Chong, Bah-Hwee Gwee
A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation. DSL (2018)
Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. IEEE Trans. Very Large Scale Integr. Syst. 26 (1) (2018)
Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin, Wei Shu, Joseph S. Chang
Single-Event-Transient Resilient Memory for DSP in Space Applications. DSL (2018)
Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer. ISCAS (2017)
Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
Highly secured state-shift local clock circuit to countermeasure against side channel attack. ISCAS (2017)
Weng-Geng Ho, Kyaw Zwa Lwin Ne, N. Prashanth Srinivas, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. ISCAS (2016)
Ali Akbar Pammu, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Nan Liu, Bah-Hwee Gwee
Success rate model for fully AES-128 in correlation power analysis. APCCAS (2016)
Weng-Geng Ho, Ali Akbar Pammu, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. ISIC (2016)
Ali Akbar Pammu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee
Interceptive side channel attack on AES-128 wireless communications for IoT applications. APCCAS (2016)
Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture. NAS (2016)
Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. ISCAS (2016)
Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
Highly secured arithmetic hiding based S-Box on AES-128 implementation. ISIC (2016)
Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. ISCAS (2016)
Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. DATE (2016)
Jize Jiang, Wei Shu, Kwen-Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Joseph Sylvester Chang, Jingyuan Liu
Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process. ISCAS (2016)
Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. ISCAS (2015)
Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). ISCAS (2015)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. IET Circuits Devices Syst. 9 (4) (2015)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. APCCAS (2014)
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (7) (2014)
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho
Synthesis of asynchronous QDI circuits using synchronous coding specifications. ISCAS (2014)
Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee
Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing. Circuits Syst. Signal Process. 33 (10) (2014)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. ISIC (2014)
Joseph S. Chang, Kwen-Siong Chong, Wei Shu, Tong Lin, Jize Jiang, Ne Kyaw Zwa Lwin, Yang Kang
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process. MWSCAS (2014)
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. ISCAS (2013)
Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
System for Wireless Sensor Networks. IEEE J. Solid State Circuits 48 (2) (2013)
Kok-Leong Chang, Joseph S. Chang, Bah-Hwee Gwee, Kwen-Siong Chong
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. IEEE J. Emerg. Sel. Topics Circuits Syst. 3 (1) (2013)
Jaeyoung Kim, Kwen-Siong Chong, Joseph Sylvester Chang, Pinaki Mazumder
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS. ACM Great Lakes Symposium on VLSI (2013)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. ISCAS (2013)
Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. ISCAS (2012)
Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. IEEE J. Solid State Circuits 47 (3) (2012)
Kwen-Siong Chong, Joseph S. Chang, Idongesit E. Ebong, Yalcin Yilmaz, Pinaki Mazumder
Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques. ISED (2012)
Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. ISCAS (2012)
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
A comparative study on asynchronous Quasi-Delay-Insensitive templates. ISCAS (2012)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. ISCAS (2011)
Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
A low-power dual-rail inputs write method for bit-interleaved memory cells. ISCAS (2011)
Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. ISCAS (2009)
Bah-Hwee Gwee, Joseph S. Chang, Yiqiong Shi, Chien-Chung Chua, Kwen-Siong Chong
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2009)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. IEEE J. Solid State Circuits 42 (9) (2007)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
Low energy 16-bit Booth leapfrog array multiplier using dynamic adders. IET Circuits Devices Syst. 1 (2) (2007)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
Design of several asynchronous-logic macrocells for a low-voltage micropower cell library. IET Circuits Devices Syst. 1 (2) (2007)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
A Low Energy FFT/IFFT Processor for Hearing Aids. ISCAS (2007)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids. IEEE Trans. Circuits Syst. II Express Briefs (9) (2006)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
A micropower low-voltage multiplier with reduced spurious switching. IEEE Trans. Very Large Scale Integr. Syst. 13 (2) (2005)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
Low-voltage micropower multipliers with reduced spurious switching. ISCAS (4) (2005)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. ISCAS (2) (2004)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
Low-voltage asynchronous adders for low power and high speed applications. ISCAS (1) (2002)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
Low-voltage micropower asynchronous multiplier for hearing instruments. ISCAS (1) (2002)