A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
Weng-Geng HoKwen-Siong ChongBah-Hwee GweeJoseph S. ChangNe Kyaw Zwa LwinPublished in: ISIC (2014)
Keyphrases
- low power
- high speed
- master slave
- power consumption
- low cost
- energy dissipation
- single chip
- high power
- cmos technology
- low voltage
- logic circuits
- wireless transmission
- low power consumption
- real time
- digital signal processing
- power reduction
- random access memory
- frame rate
- vlsi circuits
- image sensor
- embedded systems
- mixed signal
- power system
- signal processor
- nm technology
- gate array