Joseph S. Chang

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 39

Top Topics

Poses Unique Challenges

Development Kit

High Robustness

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Sun-Yang Tay, Victor Adrian, Rouli Fang, Yanshan Xie, Joseph S. Chang
A 134-μW 50-MHz Quasi-Dynamic Comparator with A Novel Clock-Free Regenerative Latch. CICC (2024)
Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. IEEE Trans. Very Large Scale Integr. Syst. 30 (9) (2022)
Yong Qu, Wei Shu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, Yue Li, Zixian Zheng, Joseph S. Chang
A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power Inputs. CICC (2021)
Yong Qu, Wei Shu, Lei Qiu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, Joseph S. Chang
A Low-Profile High-Efficiency Fast Battery Charger With Unifiable Constant-Current and Constant-Voltage Regulation. IEEE Trans. Circuits Syst. (11) (2020)
Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. ISCAS (2020)
Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller. ISCAS (2020)
Ravinder Dahiya, Deji Akinwande, Joseph S. Chang
Flexible Electronic Skin: From Humanoids to Humans. Proc. IEEE 107 (10) (2019)
Joseph S. Chang, Tong Ge
A Fully Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics With Self-Compensation for Bending: Codesign From Materials, Design, Fabrication, and Applications. Proc. IEEE 107 (10) (2019)
Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, W. Shu, Joseph S. Chang, Bah-Hwee Gwee
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. ISCAS (2019)
Yong Qu, Wei Shu, Joseph S. Chang
-Controlled Dual-Phase LED Matrix Driver for Automotive Adaptive Driving Beam (ADB) Headlighting. CICC (2019)
Yong Qu, Wei Shu, Yang Kang, Joseph S. Chang
A 30V 2A Real-Time Programmable Solid-State Circuit Breaker with Improved Detection-Speed and Enhanced Power-Efficiency. ESSCIRC (2019)
Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. AsianHOST (2019)
Yong Qu, Wei Shu, Joseph S. Chang
An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters. ISCAS (2018)
Yin Sun, Victor Adrian, Joseph S. Chang
Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters. ISCAS (2018)
Qing Liu, Wei Shu, Joseph S. Chang
A 1-GS/s 11-Bit SAR-Assisted Pipeline ADC With 59-dB SNDR in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (9) (2018)
Yin Sun, Victor Adrian, Tong Ge, Joseph S. Chang
A Circuit for Reducing the Reverse Current in DCM DC-DC Converters. DSL (2018)
Tong Ge, Zhou Jia, Joseph S. Chang
Flexible Hybrid Electronics: Review and Challenges. ISCAS (2018)
F. N. U. Juanda, Wei Shu, Joseph S. Chang
A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. IEEE Trans. Very Large Scale Integr. Syst. 26 (1) (2018)
Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin, Wei Shu, Joseph S. Chang
Single-Event-Transient Resilient Memory for DSP in Space Applications. DSL (2018)
Jize Jiang, Wei Shu, Joseph S. Chang
A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range. IEEE J. Solid State Circuits 53 (8) (2018)
Cui Keer, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2018)
Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation. ISCAS (2017)
Joseph S. Chang, Antonio F. Facchetti, Robert Reuss
Guest Editorial Organic/Printed Electronics: A Circuits and Systems Perspective. IEEE J. Emerg. Sel. Topics Circuits Syst. 7 (1) (2017)
Yin Sun, Victor Adrian, Joseph S. Chang
A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters. ISCAS (2017)
Cui Keer, Victor Adrian, Yin Sun, Bah-Hwee Gwee, Joseph S. Chang
A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters. NEWCAS (2017)
Jize Jiang, Wei Shu, Joseph S. Chang
A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point. IEEE J. Solid State Circuits 52 (3) (2017)
Tong Ge, Jia Zhou, Yang Kang, Joseph S. Chang
Review: A fully-additive printed electronics process with very-low process variations (Bent and unbent substrates) and PDK. ISCAS (2017)
Joseph S. Chang, Antonio F. Facchetti, Robert Reuss
A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches. IEEE J. Emerg. Sel. Topics Circuits Syst. 7 (1) (2017)
Qing Liu, Wei Shu, Joseph S. Chang
A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Jia Zhou, Tong Ge, Joseph S. Chang
Printed Electronics: Effects of Bending and a Self-Compensation Means. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2017)
F. N. U. Juanda, Wei Shu, Joseph S. Chang
A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands. IEEE Trans. Circuits Syst. II Express Briefs (1) (2017)
Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network. ISIC (2016)
Tong Ge, Huiqiao He, Jia Zhou, Yang Kang, Joseph S. Chang
An investigation of THD of a BTL Class D amplifier. ISCAS (2016)
Yang Kang, Tong Ge, Huiqiao He, Joseph S. Chang
A review of audio Class D amplifiers. ISIC (2016)
Jia Yu, Tong Ge, Huiqiao He, Joseph S. Chang
Substrate thickness effect on transformer. ISIC (2016)
Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. ISCAS (2016)
Jia Zhou, Tong Ge, Joseph S. Chang
Fully-additive printed electronics: Process Development Kit. ISCAS (2016)
Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. ISCAS (2015)
Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). ISCAS (2015)
Huiqiao He, Yang Kang, Jia Yu, Linfei Guo, Tong Ge, Joseph S. Chang
A novel low-power high-efficiency 3-state filterless bang-bang class D amplifier. ICECS (2015)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. IET Circuits Devices Syst. 9 (4) (2015)
Linfei Guo, Tong Ge, Joseph S. Chang
An Ultralow-Power Overcurrent Protection Circuit for Micropower Class D Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs (10) (2015)
Yin Sun, Victor Adrian, Joseph S. Chang
Design of a variable-delay window ADC for switched-mode DC-DC converters. ISCAS (2015)
Tian-Shun Ng, Yin Sun, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
Design of an output stage for high switching frequency DC-DC converters. ISIC (2014)
Huiqiao He, Tong Ge, Linfei Guo, Joseph S. Chang
An investigation into the effect of carrier generators on power supply noise in PWM Class D amplifiers. MWSCAS (2014)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. APCCAS (2014)
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (7) (2014)
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho
Synthesis of asynchronous QDI circuits using synchronous coding specifications. ISCAS (2014)
Salma Nashit, Victor Adrian, Cui Keer, Quoc-An Mai, Bah-Hwee Gwee, Joseph S. Chang
A self-oscillating class D audio amplifier with dual voltage and current feedback. ISIC (2014)
Tong Ge, Joseph S. Chang, Tong Lin, Lei Zhang, Lim Geok Soon
Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag. MWSCAS (2014)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. ISIC (2014)
Joseph S. Chang, Kwen-Siong Chong, Wei Shu, Tong Lin, Jize Jiang, Ne Kyaw Zwa Lwin, Yang Kang
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process. MWSCAS (2014)
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. ISCAS (2013)
Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
System for Wireless Sensor Networks. IEEE J. Solid State Circuits 48 (2) (2013)
Kok-Leong Chang, Joseph S. Chang, Bah-Hwee Gwee, Kwen-Siong Chong
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. IEEE J. Emerg. Sel. Topics Circuits Syst. 3 (1) (2013)
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. ISCAS (2013)
Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. ISCAS (2012)
Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. IEEE J. Solid State Circuits 47 (3) (2012)
Kwen-Siong Chong, Joseph S. Chang, Idongesit E. Ebong, Yalcin Yilmaz, Pinaki Mazumder
Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques. ISED (2012)
Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. ISCAS (2012)
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
A comparative study on asynchronous Quasi-Delay-Insensitive templates. ISCAS (2012)
Joseph S. Chang, Tong Ge, Edgar Sánchez-Sinencio
Challenges of printed electronics on flexible substrates. MWSCAS (2012)
Tong Ge, Joseph S. Chang
Filterless class D amplifiers: power-efficiency and power dissipation. IET Circuits Devices Syst. 4 (1) (2010)
Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee
A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2010)
Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee
A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2009)
Bah-Hwee Gwee, Joseph S. Chang, Yiqiong Shi, Chien-Chung Chua, Kwen-Siong Chong
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2009)
Tong Ge, Joseph S. Chang
Bang-Bang Control Class D Amplifiers: Total Harmonic Distortion and Supply Noise. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2009)
Tong Ge, Joseph S. Chang
Bang-Bang Control Class-D Amplifiers: Power-Supply Noise. IEEE Trans. Circuits Syst. II Express Briefs (8) (2008)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. IEEE J. Solid State Circuits 42 (9) (2007)
Chong-Fatt Law, Bah-Hwee Gwee, Joseph S. Chang
Optimized Algorithm for Computing Invariants of Ordinary Petri Nets. ACIS-ICIS (2006)
Meng Tong Tan, Hock-Chuan Chua, Bah-Hwee Gwee, Joseph S. Chang
An investigation on the parameters affecting total harmonic distortion in class D amplifiers. ISCAS (2000)
Meng Tong Tan, Joseph S. Chang, Yit Chow Tong
A process-independent threshold voltage inverter-comparator for pulse width modulation applications. ICECS (1999)