A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS.
Qing LiuWei ShuJoseph S. ChangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
- power consumption
- power dissipation
- cmos technology
- nm technology
- low power
- power reduction
- power saving
- clock gating
- low voltage
- single chip
- energy saving
- vlsi circuits
- silicon on insulator
- digital signal processing
- parallel processing
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- low cost
- power supply
- logic circuits
- synthetic aperture radar
- input output
- design methodology
- hd video
- case study