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Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.

Kwen-Siong ChongAparna ShreedharNe Kyaw Zwa LwinNay Aung KyawWeng-Geng HoChao WangJun ZhouBah-Hwee GweeJoseph S. Chang
Published in: AsianHOST (2019)
Keyphrases
  • secret key
  • countermeasures
  • asynchronous circuits
  • smart card
  • high speed
  • information security
  • delay insensitive
  • neural network
  • logic programming
  • modal logic
  • real time
  • classical logic
  • fault model