Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer.
Weng-Geng HoKwen-Siong ChongBah-Hwee GweeJoseph S. ChangPublished in: IET Circuits Devices Syst. (2015)
Keyphrases
- delay insensitive
- low power
- power consumption
- low cost
- high speed
- high power
- asynchronous circuits
- single chip
- digital signal processing
- logic circuits
- signal processing
- vlsi architecture
- low power consumption
- wireless transmission
- image sensor
- high frequency
- gate array
- signal processor
- real time
- vlsi circuits
- shift register
- cmos technology
- image processing algorithms